1. Technical Field
Embodiments generally relate to flash memory devices. More particularly, embodiments relate to the repurposing of a NAND memory device Ready/Busy contact as a completion interrupt.
2. Discussion
Computing systems typically store data to different types of storage media and devices. In certain cases, such as in high capacity data storage situations, multiple NAND flash chips may be coupled to a host device such as a chipset. The chipset can include a Ready/Busy (R/B#) input that is coupled to the R/B# pin of each of the NAND chips. For example, there might be two or four NAND chips sharing the same R/B# input to the chipset. If any of the NAND chips has a command in execution, then the R/B# input is typically pulled low. A particular challenge with such an approach may be that it is difficult to determine when a command has completed for a particular NAND chip, since the R/B# input remains low if commands are still outstanding for other chips that share that input. Accordingly, the chipset may need to poll the NAND chips with Read Status Enhanced commands in order to determine which commands have completed.
For example, the chipset might poll each NAND chip every microsecond or more to determine command completion. For a program command, the command completion time may be around 200 microseconds, but may vary widely. For an erase command, the completion time could be around two milliseconds and may also vary. These times can be 2× to 5× longer with multi-level cell NAND devices (i.e., devices with more than one bit per cell). One issue with polling is that the chipset may waste power (e.g., 200 mW in active state) when sending out Read Status Enhanced commands on such a frequent basis. Another issue can be performance loss. For example, polling for command completions every microsecond might cause commands to complete later (e.g., 500 ns) than they normally would.